In a synchronous digital system, a master or system clock is distributed to those circuits that perform synchronous functions. In order to mutually coordinate these synchronous functions, it is essential that each functional element is connected to a clock line in which the variation of the flank of a clock pulse, within narrow limits, will occur simultaneously with the occurrence of a corresponding flank on remaining distributed clock pulses that occur in other functional elements. The time difference between the flank of a clock pulse on a clock line and a corresponding flank of a corresponding clock pulse on another clock line, where both of the clock pulses are derived from the same master or system clock, is called skew and is measured in nanoseconds.
Since a single master clock is unable to drive a large number of driver circuits in a synchronous system, groups of local clock lines are produced from the main clock pulse, by utilizing driver circuits which each consist of a plurality of buffer units. Skew is caused by the difference in the response time of different driver circuits.
A method and an arrangement of the kind defined in the introduction are described in European Patent Application No. 0,362,691. This known arrangement includes two driver circuits from which a total of six clock signals is obtained. These six clock signals have a delay which amounts to the total or combined delay of each of the two driver circuits. When additional clock signals are required, it is necessary to use further driver circuits. The European patent application, however, fails to disclose how this problem shall be solved.
A conceivable expansion of the principle described in the European patent application would be to duplicate the known arrangement, i.e., to use two arrangements of the kind illustrated, and connect each of the arrangements to the clock generator. This solution, however, would mean that the clock signals from the two arrangements would mutually present a delay which can vary within much wider limits than the delay occurring between the clock signals in each arrangement.
Another solution to the problem would be to manufacture driver circuits in which the number of buffer units is much greater than the four buffer units shown. Present-day technology enables a driver circuit to be produced which has up to thirty-two buffer units, wherein the skew of the driver circuit is retained within one or a few nanoseconds.
These known solutions cannot be applied, at least with a reasonable number of clock circuits and a reasonable number of driver circuits, when hundreds of IC-circuits shall be driven synchronously. Several parallel-connected driver circuits are required in order to drive the high capacitive load presented by so many IC-circuits. Circuit manufacturers offer solutions with matched circuits or special clock drivers and are able to guarantee a smallest skew between different circuits, although this solution is not sufficiently effective when hundreds of IC-circuits are to be driven synchronously.